The present invention relates to architectures for integrated circuits and in particular to an improved method and apparatus providing reliable and power conserving, low-voltage operation of the cache structures.
Current computer architectures employ a set of intermediate memories (cache memories) between the processor and a main solid-state memory. A cache memory provides high-speed local storage for the processor that may help overcome the relatively slower access speeds available between the processor and the main solid-state memory. Successful operation of the cache memory takes advantage of the ability to predict likely future use of data by the processor so that data required by the processor may be pre-stored or retained in the cache memory to be quickly available when that data is needed.
Often multiple hierarchical cache memories are be used with the smallest and fastest cache (L1) operating in coordination with successively larger and slower caches (L2, L3) the largest of which is designated the “last-level cache” (LLC). Multiple levels of cache memories allow a flexible trade-off between speed of data access and the likelihood that the requested data will be in the cache memory (a cache hit). Caches are normally managed by a cache controller, which determines which portions of the cache “lines” should be ejected when new data is required in response to a cache miss, for example, and which keeps track of “dirty” cache lines in which the processor has written data to the cache, which must be reflected back into the main computer memory.
With increased circuit density in integrated circuits, power efficiency has become a design priority for high-performance and low-power processors. The maximum speed of high-performance processors is often limited by problems of power dissipation which may be addressed by improving energy efficiency. For low-power processors, energy efficiency increases the operating time of the processor when operating on battery power source.
An effective technique to increase processor efficiency is dynamic voltage and frequency scaling (DVFS) in which the processor voltage and processor clock speed are reduced at times of low processing demand. Reducing the processor voltage and frequency significantly lowers dynamic and static power consumption of transistors.
The minimum voltage (VDDMIN) that may be used with DVFS for cache memories is determined by the lowest voltage at which the transistor circuitry of the memory cells of the cache may maintain their logical state. VDDMIN may be reduced by increasing the size of the transistors in the SRAM cells of the cache memories. This makes the transistors less sensitive to mismatches induced by process variations such as random dopant fluctuations (RDF) and line edge roughness (LER) limits. Increasing the size of these transistors, however, is undesirable because cache memories currently occupy more than 50 percent of the total area for many processor systems.